Advancing Semiconductor Energy Efficiency Through Joint Microelectronics Research

The technical collaboration involves the joint development of advanced microelectronics architectures utilizing fully depleted silicon-on-insulator (FD-SOI) technology. Operating within the FAMES Pilot Line framework, which is funded by the European Commission and participating Member States under the Chips JU, this digital infrastructure initiative targets energy-efficient, sovereign semiconductor fabrication. The primary application areas for these high-reliability semiconductor substrates encompass mobile devices, automotive microcontrollers, satellite communications, edge artificial intelligence (AI), and radio frequency (RF) design for 5G/6G power amplifiers.

Mitigating Power and Performance Limitations in Planar Bulk Silicon
Industrial automation and processing nodes require an optimized balance of performance, power dissipation, and production cost. Traditional planar bulk silicon transistors exhibit significant sub-threshold leakage currents and short-channel effects when scaled down, which limits their energy efficiency in severe-duty processing loops.

To overcome these structural layout vulnerabilities, a joint technical approach is necessary to mature advanced substrate techniques. This complexity requires the combination of CEA-Leti's foundational microelectronics research capabilities with GlobalFoundries’ industrial manufacturing expertise to scale early-stage research into reproducible, high-reliability silicon platforms.

Architecture of the Joint FD-SOI System and Engineering Delegations
The technology relies on an ultra-thin layer of silicon over a buried oxide (BOX) insulator layer. This architecture provides an electrostatic channel control mechanism without requiring heavy channel doping, minimizing statistical threshold voltage variability. Responsibilities are split between the partners to leverage complementary field experience:

The structural solution optimizes runtime performance by delivering low nominal power consumption and inherent radiation tolerance. This performance parameter allows the devices to match the throughput of 14/16nm FinFET nodes for specific workloads while lowering the overall thermal envelope.

Scaling Embedded Non-Volatile Memory and Heterogeneous Integration
The implementation phase focuses on integrating these next-generation FD-SOI substrate innovations with existing semiconductor manufacturing protocols. The partners are leveraging the FAMES Pilot Line to scale advanced engineering programs across several distinct layout constraints:

These integration phases ensure process stability and long-term maintainability for cybersecure and high-reliability components deployed in demanding field environments.

Edited by Sucithra Mani, Induportals editor – adapted by AI.

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